1. Field of the Invention
The present invention relates to data processing systems utilizing cache memories, and more particularly to programming access to cache memory.
2. Art Background
Caches are used in various forms to reduce the effective time required by a processor to access instructions or data that are normally stored in main memory. The theory of a cache is that a system attains a higher speed by using a small portion of very fast memory as a cache along with a larger amount of slower main memory. The cache memory is usually placed operationally between the data processing unit or units and the main memory. When the processor needs to access information, it looks first to the cache memory to see if the information required is available in the cache. When data and/or instructions are first called from main memory, the information is stored in cache as part of a block of information taken from consecutive locations of main memory. During subsequent memory accesses to the same addresses, the processor interacts with the fast cache memory rather than main memory. Statistically, when information is accessed from a particular block in main memory, subsequent accesses will call for information from within the same block. This locality of reference property results in a substantial decrease in average memory access time.
Caches work well under the assumption that consecutively executed instructions will continue to call for information from the same area of main memory. However, cache accesses are probabilistic in nature in that many codes do not follow this pattern, but rather attempt to access one portion of main memory, then another, and then eventually return to the first portion of memory. This property is especially evident in numerical analysis and array processing codes. This skipping around causes large portions of code and data to be pushed out of the cache, only to be called for later in the processing cycle. Consequently, for these types of codes memory access time is slowed drastically as the same information is cached, flushed out of the cache and then recached repeatedly.
Many codes have predictable patterns of memory access. However, conventional caching methods do not take advantage of this fact to make the caching of memory locations more deterministic and less probabilistic in nature. Although some methods, like that used in the i860.TM. processor from Intel Corporation, Santa Clara, Calif., permit the user to disallow certain areas of memory from being cached, this method certainly does not decrease memory access time. Accordingly, it would be desirable to have a caching method that takes advantage of predictable patterns of memory access of certain software codes in order to increase the efficiency of memory accesses.